The present invention relates to an apparatus and method for making electrical connections between a conductive region through an insulating layer and more particularly to a method for use in the manufacture of semiconductor devices which prevents charge accumulation during exposure by a charged beam.
The use of charged beams, such as electron beams, in manufacturing processes has been known for many years. For example, in the manufacturing of various types of semiconductor devices, an electron beam is scanned to provide accurate exposure of a pattern. The electron beam processes are generally more accurate than other forms of pattern generation. In one example using electron beam technology, a semiconductor wafer to be processed is coated with an electron beam resist. The wafer is usually formed by a semiconductor material such as doped silicon covered by a silicon dioxide or other insulating layers. The semiconductor wafer, including the silicon dioxide layer and the resist layer, are placed in a metal holder prior to exposure by the electron beam. The holder-mounted wafer is then placed in an electron beam exposure apparatus. The electron beam apparatus normally includes automatic means for controlling the deflection of the electron beam and hence for controlling the position of the electron beam as it impinges upon the resist-covered wafer. The deflecting (or scanning) of the electron beam causes a pattern to be exposed in the electron beam resist coated on the surface of a wafer.
In a typical example, the electron beam is incident upon the resist with a spot diameter of one-half micron and the electron beam spot is deflectable to an accuracy of 0.02 micron or better. Such an accuracy in an electron beam apparatus is readily achievable with conventional electron beam systems currently available from manufacturers. While the inherent high accuracy of the electron beam apparatus has lead to semiconductor processing steps which achieve semiconductor device patterns having similar high accuracy, certain problems have resulted due to the charge accumulation in a semiconductor wafer caused by the electron beam.
A wafer to be exposed includes a conductive region (such as a semiconductive region or base formed by doped silicon), includes an insulator (such as silicon dioxide), and includes an electron beam resist layer. When the wafer is exposed to an electron beam, a charge accumulation occurs in the conductive region. The charge accumulation occurs because electrons from the incident electron beam are injected through the electron beam resist layer, through the insulating layer and into the conductive region. If the conductive region is not connected through a conductive channel to a charge sink, then a charge is accumulated in the conductive region. The magnitude of the charge is generally a function, among other things, of the current in the incident electron beam, the duration of charge accumulation, and the conductivity between the conductive region and a discharge sink. Any accumulated charge, of course, produces an unwanted electrostatic field. Although the charge distribution within the conductive region may be generally uniform, the electrostatic field pattern outside the semiconductor wafer, and through which the electron beam must pass, is not uniform. The magnitude of the electrostatic field varies as a function of the position of the wafer with respect to the incident electron beam in a plane normal to the incident electron beam. The charge accumulation in some examples has been observed to be several hundred volts or more, causing a deflection error of the electron beam with respect to the wafer of 15 microns or more. When it is desired to obtain positional accuracies of 0.1 micron or beter, an accumulated charge-caused positional error of 15 microns is, of course, intolerable.
In order to avoid or reduce the problem of accumulated charge-caused positional error, attempts have been made to conduct away the charge from the conductive region. One technique to avoid the problem employs etching away of the insulating layer to expose the conductive region thereby allowing electrical contact to the conductive region during electron beam exposure. In one process, the edge of the insulated wafer is dipped in an etching solution to remove the insulator and to permit contact to the conductive region. Such a step is generally unsatisfactory in that it is cumbersome and often results in contamination of the wafer surface. In order to help avoid contamination of the wafer surface, a special etching on the back side of the wafer has been employed. The back side etching is carried out by floating the wafer on the etching solution to dissolve the insulating layer formed on the back surface of the wafer. Such a float-etching process is cumbersome and when employed, it is still difficult to keep the top surface uncontaminated. None of the etching processes have proved entirely satisfactory.
In addition to the etching processes, mechanical abrasion or drilling steps have been attempted in order to penetrate the insulating layer in order to make electrical contact to the conductive region. These mechanical steps, however, form a dust from the abraded material which tends to contaminate the wafer surface.
Other mechanical and chemical methods of making electrical connection to the conductive region have not proved satisfactory and hence there is a need for an improved method and apparatus for forming electrical contact to a conductive region covered by an insulating layer. The improved method and apparatus is desirably one which is readily integrated into the conventional semiconductor processing steps.